Roles & Responsibilities: –

Chip-level DFT insertion with sound knowledge of scan compression, ATPG MBIST & JTAG techniques

Should have good post silicon DFT bringup debug experience

Hands on in multi vendors DFT tools

Create test plan for complex ASICs and drive the DFT implementation & verification

Ability to guide people, multiplex many issues and set priorities

Good communications and leadership skills

Job Location: Hyderabad
Experience (Years): 4-15 Years

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